This invention relates generally to semiconductor circuits, and more specifically, to semiconductor capacitor structures.
Integrated circuits use a variety of known interconnect capacitor structures for their excellent linearity and high quality factor, Q. These capacitors are essential components in many analog, mixed signal and RF integrated circuits. Such capacitors typically use multiple metal layers to form a parallel plate or a parallel finger capacitor. The parallel plates or parallel fingers are arranged in an array structure and consume a significant amount of circuit area because of their relatively low capacitive density. These capacitors rely on or partially rely on vertical inter-layer capacitive coupling and therefore do not take full advantage of semiconductor lithography and IC process technology. As a consequence, these capacitors have relatively low capacitance density and thus consume a considerable amount of circuit area. For example, in a vertical direction, circuit cross talk imposes a severe limit to the minimum dielectric thickness which often stays unchanged for several technology generations. In a lateral direction, the plates and fingers are separated by a minimum space determined primarily from lithography and process capability. This minimum spacing is typically much smaller than the interlayer dielectric thickness, leading to a larger lateral capacitive coupling (or lateral flux) in modern IC process technologies. In addition, as IC pattern transfer technologies improve, uniformity control of dielectric thickness also becomes less precise than lateral pattern definition.
In the past, one form of capacitor structure used horizontal parallel metallic bars or fingers separated by a dielectric material. The capacitance of such structures consists of both lateral and vertical capacitive coupling. Since the vertical capacitive coupling does not scale as technology advances, the capacitive density is not optimized to present-day technology capability. To obtain more lateral capacitive coupling, alternative capacitor structures have been proposed including vertical stacks placed in orthogonal coordinates and fractal structures. These capacitors have either a relatively large terminal loss due to the necessity of having to terminate in different metal layers or suffer from corner rounding errors that reduce desired capacitance.